Journal article
2024
APA
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Chang, K., Singh, S., Claes, J., Sahay, K., Teoh, J., & Puri, S. (2024). Surface Code with Imperfect Erasure Checks.
Chicago/Turabian
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Chang, Kathleen, Shraddha Singh, Jahan Claes, Kaavya Sahay, James Teoh, and S. Puri. “Surface Code with Imperfect Erasure Checks” (2024).
MLA
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Chang, Kathleen, et al. Surface Code with Imperfect Erasure Checks. 2024.
BibTeX Click to copy
@article{kathleen2024a,
title = {Surface Code with Imperfect Erasure Checks},
year = {2024},
author = {Chang, Kathleen and Singh, Shraddha and Claes, Jahan and Sahay, Kaavya and Teoh, James and Puri, S.}
}
Recently, a lot of effort has been devoted towards designing erasure qubits in which dominant physical noise excites leakage states whose population can be detected and returned to the qubit subspace. Interest in these erasure qubits has been driven by studies showing that the requirements for fault-tolerant quantum error correction are significantly relaxed when noise in every gate operation is dominated by erasures. However, these studies assume perfectly accurate erasure checks after every gate operation which generally come with undesirable time and hardware overhead costs. In this work, we investigate the consequences of using an imperfect but overhead-efficient erasure check for fault-tolerant quantum error correction with the surface code. We show that, under physically reasonable assumptions on the imperfect erasure checks, the threshold error rate is still at least over twice that for Pauli noise. We also study the impact of imperfect erasure checks on the effective error distance and find that it degrades the effective distance under a general error model in which a qubit suffers from depolarizing noise when interacting with a leaked qubit. We then identify a more restrictive but realistic noise model for a qubit that interacts with a leaked qubit, under which the effective error distance is twice that for Pauli noise. We apply our analysis to recently proposed superconducting dual-rail erasure qubits and show that achieving good performance surface code quantum memories with relaxed system requirements is possible.